In recent years, flat displays are used in various products and fields. For example, an EL (electroluminescent) display panel is known as one of bonding substrates used in such flat displays.
An EL substrate, which is used in an EL (organic EL/inorganic EL) display panel, has a configuration in which a transistor such as a TFT (thin film transistor) is provided on a substrate, and an EL element (organic EL element or inorganic EL element) that is electrically connected with the transistor is further provided on the substrate.
In the EL substrate, (i) a plurality of gate lines and a plurality of source lines for supplying various signals to pixels and (ii) a plurality of driving power source lines are provided. Each of the pixels which is surrounded by the gate line, the source line, and the driving power source line, is provided with a switching transistor, a driving transistor, a Cs (capacitor) section, and the EL element.
Each of the switching transistor, the driving transistor, the Cs section, and the EL element has a multi-layer structure in which each of layers is formed by photolithography with the use of a photomask.
The following description will discuss a method for producing an organic EL substrate as an example of a method for producing an EL substrate.
(a) through (i) of FIG. 18 are cross-sectional views partially and sequentially illustrating processes for producing an organic EL display panel disclosed in Patent Literature 1.
In Patent Literature 1, first, a gate metal 302 is formed as one solid film on an insulating substrate 301 (see (a) of FIG. 18).
Then, the gate metal 302 is patterned with the use of a first photomask so as to form a gate electrode 302G, a signal line 302L, and a lower part electrode of a Cs (capacitor) section (not illustrated) which are made of the gate metal 302 (see (b) of FIG. 18). Then, a gate insulating film 303, a semiconductor layer 304 made of amorphous silicon or polysilicon, and an insulating layer 305 made of silicon nitride or silicon oxide are formed on the insulating substrate 301 as one solid film covering the gate electrode 302G and the signal line 302L.
Next, the insulating layer 305 is patterned with the use of a second photomask so as to form a channel protective film 305a (see (c) of FIG. 18).
Then, an n+ silicon layer 306 is formed as one solid layer on the semiconductor layer 304 so as to cover the channel protective film 305a (see (d) of FIG. 18). Subsequently, a hole is formed in the gate insulating film 303, the semiconductor layer 304, and the n+ silicon layer 306 with the use of a third photomask so that the gate metal 302 is exposed at a location at which a contact hole is to be formed.
After that, a source metal 307 is formed as one solid film (see (e) of FIG. 18). In this case, the gate metal 302 and the source metal 307 are bonded to each other via the hole formed in the gate insulating film 303, the semiconductor layer 304, and the n+ silicon layer 306, and thus a contact hole (not illustrated) is formed.
Then, the source metal 307 is patterned with the use of a fourth photomask so as to form an upper part electrode of the Cs section (not illustrated), a source electrode 307S, a drain electrode 307D, a scanning line (not illustrated), and a driving power source line (not illustrated) (see (f) of FIG. 18).
Moreover, in this case, the semiconductor layer 304 and the n+ silicon layer 306 are patterned with the use of the fourth photomask so as to form (i) a semiconductor film 304a which is made up of the semiconductor layer 304 and (ii) impurity semiconductor films 306a and 306b which are made up of the n+ silicon layer 306.
Next, a conductive film is formed by vapor phase growth and is then patterned with the use of a fifth photomask so as to form a pixel electrode 308 (see (g) of FIG. 18).
Subsequently, a protective film 309 is formed as one solid film which covers the source electrode 307S, the drain electrode 307D, the upper part electrode of the Cs section (not illustrated), the scanning line, the driving power source line, and the pixel electrode 308, and then an opening 309a is formed in the protective film 309 with the use of a sixth photomask so that the pixel electrode 308 is exposed via the opening 309a (see (h) of FIG. 18).
In Patent Literature 1, after that, one solid film of a resin such as a polyimide is applied to an upper part of the protective film 309 and the pixel electrode 308 (see (i) of FIG. 18), and then a netlike insulating film 310 is formed with the use of a seventh photomask. Thus, a partition wall 311 made up of the protective film 309 and the netlike insulating film 310 is formed, and then an organic EL layer (not illustrated) is formed on the pixel electrode 308, and further a counter electrode (not illustrated) is formed on the organic EL layer. Further, a sealing layer is formed by applying a resin (such as an epoxy resin; a thermosetting resin such as an acrylic resin; a thermoplastic resin; or a photo-curable resin) to the counter electrode, and hardening the resin.
As such, in Patent Literature 1, the 6 photomasks are used before the opening 309a is formed in the protective film 309.